1. Field of the Invention
This invention relates in general to the field of instruction execution in computers, and more particularly to an apparatus and method for executing a paired compare-and-branch operation within a single integer pipeline.
2. Description of the Related Art
Conditional jump instructions are common to all present day microprocessor instruction sets. A conditional jump instruction allows a programmer to direct a microprocessor to evaluate the state of the microprocessor or particular attributes of a previously generated result at a certain point in an application program. Programmers employ conditional jump instructions to redirect the flow of an application program based upon the findings of the evaluation. Most often, a conditional jump instruction specifies that the contents of a result status register, or flags register, are to be evaluated against a prescribed criteria. The flags register contains bits, or flags, that are set when a result is generated by the microprocessor. The flags are set to indicate the condition of the result. For example, an instruction directing the microprocessor to add two operands is executed by generate a result. Accordingly, the flags register is updated to reflect attributes of the generated sum. For example, if the sum is zero, then a zero flag in the flags register is set. If the sum is a negative number, then a sign flag is set to indicate that the sum is negative. Consequently, the conditional jump instruction provides a programmer with the flexibility to make program control decisions based upon certain attributes, or conditions, of a generated result without having to specifically examine the result itself. The programmer may desire to direct program control to another location if the result is zero, in which case he/she would program a conditional jump instruction immediately following the instruction that generates the result where the conditional jump instruction prescribes a jump, or branch, to a target address if the zero flag in the flags register is set.
In many cases, a conditional jump decision is not made based upon an explicitly generated result, but rather upon a comparison of two operands. For example, a conditional jump decision can be made based upon whether a first operand is equal to a second operand. In this example, the only knowledge of the two operands that is required to make the jump decision is whether they are equal; no xe2x80x9cresultxe2x80x9d is necessarily required. For situations such as this, microprocessor instruction sets provide a compare instruction. The compare instruction enables a programmer to specify two operands to be compared and, upon execution of the compare instruction, the outcome of the comparison is reflected by updating to the flags register. To accomplish the comparison, some microprocessors subtract the first operand from the second operand; other microprocessors utilize a different comparison technique altogether to derive attributes that distinguish the two operands. Regardless of what approach is used to make the comparison, it is the bits within the flags register that describe the comparison result.
Compare instructions rarely occur in isolation in an application program. This is because operands are typically compared in order to make some type of decision based upon the result of their comparison. Hence, instead of finding a stand-alone compare instruction in an application program, it is much more common to find a compare instruction that is immediately followed by a conditional jump instruction. In fact, this combination of macro instructions is so commonly encountered that the operation prescribed by these two instructions in combination together is referred to as a compare-and-branch operation or compare/branch operation.
A present day microprocessor is divided into stages, with each stage dedicated to performing a specific function. A first stage fetches program instructions from memory and places them in a macro instruction queue. A following stage decodes these macro instructions into associated micro instructions. Decoded micro instructions are then executed in sequence by subsequent stages of the microprocessor in synchronization with a microprocessor clock signal. This decoding, or translation, of macro instructions into micro instructions is required primarily to permit legacy application programs to execute on newer microprocessors. In fact, the x86 instruction set architecture still maintains the same macro instructions today as were initially provided during the late 1970""s.
The format and syntax of macro instructions provide for structured and standardized software engineering practices, thus fostering the production of application programs that can be executed on a number of different microprocessors. In contrast, micro instructions are deliberately designed to operate such that the capabilities of a specific microprocessor are exploited and its limitations are circumvented. Accordingly, a micro instruction will never prescribe a task that logic within a given stage of the microprocessor cannot perform. In reality, one most often finds that a single macro instruction must be translated into several micro instructions, each of the micro instructions directing the microprocessor to perform a certain task, the aggregate of which accomplish the operation prescribed by the single macro instruction.
Because of this complexity surrounding the translation of macro instructions into corresponding micro instructions, a present day pipeline microprocessor typically does not attempt to combine two or more macro instructions into a single micro instruction. Hence, what transpires when a programmed compare-and-branch operation is encountered is that two micro instructions are generated: a first compare micro instruction corresponding to the compare macro instruction and a second conditional jump micro instruction corresponding to the conditional jump macro instruction.
What""s more, the continued proliferation of microprocessors into the marketplace has only served to significantly expand the requirements for faster and more efficient performance. And certainly, there are microprocessors, such as Intel""s Pentium(copyright) III, that provide multiple execution pipelines that are capable of executing macro instructions in parallel. But these microprocessors are very costly to manufacture and result in a design that is much more complex than the traditional single execution pipeline.
Within a single pipeline microprocessor, combination of the compare operation with the jump operation has not been heretofore achievable because both operations require the same logic resources to update and to access the flags register. Consequently, the two tasks must be performed in sequence by two separate micro instructions because logic within only one pipeline stage is dedicated to reading and writing the flags register.
The present inventors have, however, observed that a most micro instruction formats can accommodate a single micro instruction that can prescribe both the compare task and the conditional jump task for compare/branch operations when the compare task prescribes register operands only. What is currently lacking is the logic for pairing the two macro instructions within early pipeline stages and the apparatus in later pipeline stages that permits one stage to update the flags register with the result of the comparison and logic in a following stage that is capable of reading the flags register to resolve the conditional jump.
Therefore, what is needed is a single pipeline microprocessor for executing a compare-and-branch operation by employing a single compare/branch micro instruction.
In addition, what is needed is an apparatus in a single pipeline microprocessor that is capable of executing a compare/jump operation much faster than has heretofore been provided.
It is a feature of the present invention to provide a microprocessor, having a single integer pipeline, for performing a compare-and-branch operation. The microprocessor includes translation logic and execute logic. The translation logic receives a compare macro instruction and a conditional jump macro instruction, and generates a compare-and-branch micro instruction directing the microprocessor to make a comparison and to perform a conditional branch based upon a result of the comparison. The execute logic is coupled to the translation logic. The execute logic makes the comparison and generates the result.
In another aspect, it is a feature of the present invention to provide an apparatus in a single pipeline microprocessor for executing a compare-and-branch operation. The apparatus has a jump combiner, compare execution logic, and jump resolution logic. The jump combiner pairs a compare instruction and a conditional jump instruction into a compare/branch micro instruction. The compare/branch micro instruction prescribes a comparison task and a conditional branch task. The compare execution logic is coupled to the jump combiner. The compare execution logic receives the compare/branch micro instruction, it performs the comparison task, it generates a result of the comparison task, and it updates bits in a flags register to describe the result. The jump resolution logic is coupled to the compare execution logic. The jump resolution logic evaluates one or more of the bits to resolve the conditional branch task.
In a further aspect, it is a feature of the present invention to provide an apparatus for executing a macro instruction sequence that directs a microprocessor to compare two register operands, to update a flags register to describe a comparison result, to evaluate the flags register to determine if the comparison result satisfies a prescribed condition, and to transfer program control to a branch target address if the prescribed condition is satisfied. The apparatus includes translation logic and condition evaluation logic. The translation logic decodes the macro instruction sequence into a compare-and-branch micro instruction. The compare-and-branch micro instruction has two operand fields, an opcode field, and an immediate field. The two operand fields specify the two register operands. The opcode field specifies the prescribed condition and directs execute logic to compare the two register operands to generate the comparison result. The immediate field specifies the branch target address. The condition evaluation logic is coupled to the translation logic and evaluates the flags register.
In yet another aspect, it is a feature of the present invention to provide a method for performing a compare-and-branch operation in a pipeline microprocessor. The method includes translating a compare macro instruction and a conditional jump macro instruction into a single compare-and-jump micro instruction, performing a compare operation prescribed by the single compare-and-jump micro instruction to produce a result, and evaluating the result in accordance with a condition prescribed by the single compare-and-jump micro instruction to indicate whether or not a branch is to be taken.